In the fabrication of an Application-Specific Integrated Circuit (ASIC), a standard cell library is often used. A standard cell library may include several hundred predefined “cells”, which are predefined circuit design components that can be selectively combined using a logic design entry software tool to implement a user's circuit design. Once the logic design is entered, placement and routing tools are utilized to generate a placement and routing solution, which arranges the various interrelated cells of the logic design such that it can be fabricated on a chip, and assigns predefined routing tracks that provide signal (interconnect) lines for passing signals between the interrelated cells. A layout tool is then utilized to construct a three-dimensional representation of the actual circuit structures (e.g., regions of doped semiconductor, insulated regions, and metal lines) needed to implement the logic design. Next, this three-dimensional representation is used to generate a set of masks that are used to fabricate an integrated circuit (IC), such as an ASIC.
As the trend towards miniaturization of integrated circuits (ICs) continues, there is a need for transistors to have increasingly smaller dimensions. Fin field effect transistor (FinFET) technology is becoming more prevalent as device size continues to shrink. It is therefore desirable to have improved finFET devices and methods of fabrication.